This invention relates, in general, to monolithic integrated circuit chips containing data processors, and more particularly, to a data processor system not requiring a valid memory address enable pin.
Generally digital data processors made on a single monolithic integrated circuit chip interface with additional external memory and peripheral devices. When the processor is addressing these external devices it is necessary for the external device to know whether a read or a write operation is to be performed in addition to knowing the address. In the past, a read and a write strobe line connected to the external devices were used. Then when a read operation was to be performed a predetermined signal was transmitted on the read strobe line along with the proper address on the address output lines. For a write operation a predetermined signal was sent on the write strobe line while the proper address was sent on the address output lines.
Another scheme that is used, is to combine the read/write signals onto one line and then to use a separate line as an address enable or a valid memory address line, and then the external device can decode the signal on the two lines and determine whether a read operation or a write operation is to be performed as well as knowing that the proper address is present at the address output lines. One such scheme is described in U.S. Pat. No. 4,087,855 to Thomas H. Bennett et al.
As digital data processors, which are made on a monolithic integrated circuit chip, become more complex and must interface with more external devices, it becomes highly desirable to reduce the number of interface pins or interface lines that are needed between the digital data processor and the external devices. A reduction in the number of interface pins results in less wiring that has to be done and also allows the digital data processor to be made in a smaller or at least in a standard package.
Accordingly, it is an object of the present invention to provide a monolithic integrated circuit chip having a microprocessor which does not require that a valid memory address enable signal be sent to external devices. This results in the elimination of an interface pin.